1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor circuit that comprises a plurality of semiconductor units such as insulated gate transistors and the like, especially to that having a semiconductor circuit that comprises an active matrix unit (high withstand voltage circuit) and a logic circuit unit (high-speed driving circuit) for driving the active matrix unit both formed on one substrate, and also relates to a method for fabricating the semiconductor device. The semiconductor circuit to be constructed according to the invention may be on any insulation substrates of, for example, glass or the like, or on any insulation films as formed on semiconductor substrates of, for example, single-crystal silicon or the like.
In particular, the invention is especially favorable to and effective for semiconductor devices comprising a pixel matrix portion and a logic circuit for driving it, such as, liquid-crystal display devices, etc. The semiconductor device of the invention includes not only insulated gate transistors (semiconductor units) such as thin film transistors (TFTs), MOS transistors, etc., but also display devices having a semiconductor integrated circuit that comprises such semiconductor units, even further including electro-optical devices such as image sensors, etc. In addition, the semiconductor device of the invention still further includes electronic appliances incorporating any of those display devices and electro-optical devices.
2. Description of the Related Art
Active matrix-type liquid-crystal display devices are widely noticed in the art, which comprise a pixel matrix and a driving circuit comprising thin film transistors (TFTs) and the like as formed on an insulation substrate. Liquid-crystal panels having a size of from 0.5 to 20 inches or so are utilized as image-displaying panels.
One direction of liquid-crystalline display development is toward large-area display panels. In display devices having a large-area display panel, the pixel matrix to be the image-displaying portion shall have a large area and the source interconnections and also the gate interconnections as aligned in matrices in the circuit shall be long with the result that the circuit inevitably shall have increased interconnection resistance. In addition, the circuit must be patterned finer, for which the interconnection patterns shall be inevitably finer. Such finer interconnection patterns increase more the interconnection resistance. In each pixel, the source interconnection and the gate interconnection are connected with individual switching units such as TFTs and others. With the increase in the number of pixels, the incidental capacity increases, which, however, is problematic. In liquid-crystal display devices, in general, the gate interconnection pattern is integrated with the gate electrode pattern. In those, therefore, increasing the panel area often causes substantial gate signal delay.
If the materials constituting a gate interconnection have a lower resistivity, it is possible to modify the gate interconnection patterns to be finer and longer; therefore, enable large-area display panels. Al, Ta, Ti and the like have heretofore been used as the materials constituting the gate interconnection of those, Al is the most popular, as having a lowest resistivity and capable of being subjected to anodic oxidation. An oxide film as formed through anodic oxidation of Al has the advantage of improving the heat resistance of Al patterns coated with the oxide film. However, Al patterns are still problematic in that, even at a process temperature falling between 300xc2x0 C. and 400xc2x0 C. or so, they give whiskers and hillocks and are often deformed. In addition, Al readily diffuses into insulation films and active layers, thereby causing TFT operation failure, and TFT characteristics are much degraded by it.
For further enlarging the panel size of display devices and for ensuring finer patterning in fabricating them, needed are electrode structures having a much lower resistivity and better heat resistance.
Another direction of liquid-crystal display development is toward large scale integration of semiconductor units. For this, generally known is a peripheral driving circuit-integrated structure, for which a pixel matrix and a peripheral driving circuit are integrated and mounted on one and the same substrate. The peripheral driving circuit-integrated structure of that type has the advantages of low production cost and compact size.
As a rule, in an ordinary pixel matrix, either one of p-channel or n-channel thin film transistor (TFT) is disposed as a switching unit. A peripheral driving circuit for driving the pixel matrix comprises a logic circuit unit (high-speed driving circuit). One typical example of the peripheral driving circuit comprises a CMOS circuit unit composed of P-channel and N-channel TFTs.
For example, the TFTS disposed in the pixel matrix portion is required that each of the TFTs has a lower OFF current characteristic, because the pixel electrodes disposed in the pixel matrix portion is required to have a charge-retaining function.
On the other hand, the TFTs constituting the logic circuit disposed to be the peripheral driving circuit is required to operate quickly even at low current.
As in the above, the pixel matrix and the logic circuit differ from each other with respect to the necessary TFT characteristics for them. Therefore, it is desirable to prepare different TFT structures for the pixel matrix and the logic circuit and to fabricate the pixel matrix and the logic circuit by the use of those different TFT structures as separately prepared for them. However, the process of separately fabricating the pixel matrix and the logic circuit and integrating them is complex, and the yield in the process is low, and, in addition, the production costs are high. The complicated process to lower the yield and to increase the production costs is undesirable.
Given that situation, it is desired to form TFTs for the pixel matrix and those for the logical circuit all on one and the same substrate in a continuous process for fabricating peripheral driving circuit-integrated liquid-crystal display devices.
As one means for solving the problems noted above, known is a thin film transistor structure having an LDD (lightly doped drain) region. The LDD region is to relax the field strength to be formed between a channel forming region and a drain region, while lowering the OFF current in thin film transistors and preventing the thin film transistors from deteriorating. Having such an LDD region, thin film transistors ensure a lower OFF current characteristic.
In conventional techniques, the LDD region is formed from an anodic oxide film in a self-aligned process. However, the self-aligned process is not suitable for forming fine patterns, in which the patterned line width and the condition for anodic oxidation are difficult to control.
Given that situation in the art, the subject matter of the present invention is to provide a high-productivity method for forming plural TFTS each having a different LDD structure on one and the same substrate in a continuous manner, and to provide a semiconductor device having such plural TFTs on one and the same substrate. Specifically, the invention provides a novel TFT structure and a high-productivity method for producing it.
The first characteristic of the invention providing a novel semiconductor device structure is that the gate interconnections and the gate electrodes constituting TFT all have a multi-layered structure and are made from materials having good heat resistance. For example, a TaN film is first formed, then a Ta film is layered on it, and another TaN film is further layered on that Ta film to give a multi-layered structure in a continuous process, in which the multi-layered structure formed is coated with an inorganic film, typically with a protective film (having a thickness of from 10 to 100 nm) of silicon nitride.
The first aspect of the invention is a semiconductor device having a semiconductor circuit that comprises semiconductor units, wherein each semiconductor unit comprises;
a source region, a drain region, and a channel forming region between the source region and the drain region all formed on a substrate having an insulation surface,
a gate insulation film formed on the channel forming region at least in contact with it,
a gate electrode formed in contact with the gate insulation film, and
a protective film at least covering the upper surface and the side surface of the gate electrode.
In the semiconductor device, preferably, the gate electrode has a multi-layered structure that comprises at least one layer consisting essentially of one element selected from tantalum, molybdenum, titanium, chromium and silicon.
More preferably, the gate electrode has a three-layered structure that comprises a first layer consisting essentially of tantalum with nitrogen, a second layer consisting essentially of tantalum, and a third layer consisting essentially of tantalum containing nitrogen, as layered in that order on the substrate.
Also preferably, the channel forming region contains an element capable of promoting silicon crystallization. More preferably, the concentration of the element is higher in the source region and in the drain region than in the channel forming region.
The second aspect of the invention is a semiconductor device having a semiconductor circuit that comprises semiconductor units, wherein each semiconductor unit comprises;
a source region, a drain region, and a channel forming region between the source region and the drain region all formed on a substrate having an insulation surface,
a low-concentration dopant region formed between the source region and the channel forming region and between the drain region and the channel forming region,
a gate insulation film formed at least on the channel forming region,
a gate electrode formed above the channel forming region with being in contact with the gate insulation film, and
a protective film at least covering the upper surface and the side surface of the gate electrode, and wherein;
the gate electrode has a three-layered structure that comprises a first tantalum layer containing nitrogen, a second tantalum layer and a third tantalum layer containing nitrogen as formed on the substrate in that order,
the channel forming region contains an element capable of promoting silicon crystallization, and
the concentration of the element is higher in the source region and in the drain region than in the channel forming region.
In the semiconductor device, preferably, the gate electrode is provided with an insulator on its upper surface and side surface via the protective film thereon, and
the boundary between the low-concentration dopant region and the drain region and that between the low-concentration dopant region and the source region are determined by the insulator.
Also preferably, the gate electrode is provided with a side wall on its side surface via the protective film thereon, and
the boundary between the low-concentration dopant region and the drain region and that between the low-concentration dopant region and the source region are determined by the side wall.
Still preferably, the gate electrode is provided with a side wall directly on its side surface, and
the upper surface of the gate electrode and the side wall are covered with the protective film.
Further preferably, the source region and the drain region contain a dopant for N-type conductivity added thereto.
Again preferably, the source region and the drain region contain a dopant for N-type conductivity and a dopant for P-type conductivity added thereto.
Still again preferably, at least a part of the source region and the drain region is of a silicide.
The second characteristic of the invention is that the side wall is formed through anisotropic etching with forming the insulator (of which the size is larger than that of the side wall) via a mask. In the high-speed driving circuit portion of the semiconductor device of the invention, disposed is a TFT having an LDD structure according to a self-aligned process based on using the side wall. On the other hand, in the high withstand voltage circuit portion (the active matrix portion) therein, disposed is a TFT having an LDD structure according to a non-self-aligned process based on using the mask.
The third aspect of the invention is a semiconductor device with a semiconductor circuit of semiconductor units, having a high withstand voltage circuit comprising a first semiconductor unit and a high-speed driving circuit comprising a second semiconductor unit, both on one and the same substrate, wherein;
the high withstand voltage circuit comprises a first gate electrode, an insulator to cover the upper surface and the side surface of the first gate electrode, and a first source region and a first drain region as doped with a dopant for N-type or P-type conductivity via the insulator serving as a mask, and
the high-speed driving circuit comprises a second gate electrode, a side wall formed on the side surface of the second electrode, and a second source region and a second drain region as doped with a dopant for N-type or P-type conductivity via the side wall serving as a mask.
The fourth aspect of the invention is a semiconductor device comprising;
a multi-layered interconnection that comprises a layer of a material consisting essentially of tantalum and a layer of a metal material, the latter being layered on the former,
an interlayer insulation film as formed to cover the multi-layered interconnection, and
a metal interconnection as formed on the interlayer insulation film, wherein;
the interlayer insulation film has at least one opening, and
the multi-layered interconnection is interconnected with the metal interconnection via the opening.
The fifth aspect of the invention is a method for fabricating a semiconductor device having a semiconductor circuit comprising semiconductor units over a substrate having an insulation surface, which comprises;
a step of forming a crystalline semiconductor film over the substrate having the insulation surface,
a step of forming a gate insulation film on the crystalline semiconductor film,
a step of forming an interconnection on the gate insulation film,
a first doping step to be effected with a dopant for N- type conductivity, via the interconnection serving as a doping mask,
a step of forming a protective film to cover the interconnection,
a step of forming an insulation film to cover the interconnection and the protective film,
a step of forming a mask partly over the insulation film,
a step of anisotropically etching the insulation film to form a nearly triangular insulator on the side surface of the interconnection with the insulator below the mask being left as such,
a second doping step to be effected via the nearly triangular insulator, the remained insulator and the gate electrode all serving as doping masks, for which the dopant concentration is higher than that for the first doping step, and
a heat treatment step for gettering an element used in the step of forming the crystalline semiconductor film, the element promoting crystallization of a semiconductor film.
The sixth aspect of the invention is a method for fabricating a semiconductor device having a semiconductor circuit comprising semiconductor units over a substrate having an insulation surface, which comprises;
a step of forming a crystalline semiconductor film over the substrate having the insulation surface,
a step of forming a gate insulation film on the crystalline semiconductor film,
a step of forming an interconnection on the gate insulation film,
a step of forming an insulation film to cover the interconnection,
a step of forming a mask partly over the insulation film,
a step of anisotropically etching the insulation film to form a nearly triangular insulator on the side surface of the interconnection with the insulator below the mask being left as such, and
a step of doping with a dopant for N-type conductivity or with a dopant for P-type conductivity via the nearly triangular insulator, the insulator below the mask and the gate electrode all serving as doping masks.
In the fifth and sixth aspects of the invention, preferably, the step of forming an interconnection on the gate insulation film comprises forming a first tantalum layer containing nitrogen, a second tantalum layer, and a third tantalum layer containing nitrogen in that order on the substrate in a continuous manner, followed by patterning the resulting multi-layered structure.
Also preferably, in the fifth and sixth aspects, the step of forming the crystalline semiconductor film comprises;
forming an amorphous semiconductor film to be in direct contact with the insulation surface of the substrate,
contacting the amorphous semiconductor film with an element capable of promoting crystallization of the amorphous semiconductor film, and
crystallizing the amorphous semiconductor film through heat treatment to convert it into the crystalline semiconductor film.
Also preferably, in the fifth and sixth aspects, the step of forming the crystalline semiconductor film comprises;
forming an amorphous semiconductor film to be in direct contact with the insulation surface of the substrate,
contacting the amorphous semiconductor film with an element capable of promoting crystallization of the amorphous semiconductor film, and
crystallizing the amorphous semiconductor film through laser irradiation to convert it into the crystalline semiconductor film.